1. Technical Field
The present invention generally relates to a semiconductor memory apparatus, and more particularly, to a method and system for processing a repair address in a semiconductor memory apparatus.
2. Related Art
A flash memory apparatus is a kind of nonvolatile memory apparatus that includes a configuration information storage block for storing configuration data. The configuration information storage block is assigned to a specified block of a memory device and is composed of a plurality of nonvolatile memory cells. For reference, such a configuration information storage block is called a code address memory (CAM).
Since a flash memory apparatus may have bad memory cells, spare memory cells are used in place of the bad memory cells. Accordingly, addresses for the bad memory cells are mapped to spare memory cells. In this way, a flash memory apparatus need not be wasted because a few memory cells are bad. Memory cells may be tested as part of manufacturing process to determine which memory cells are bad. Memory cells may also be tested and flagged as bad by an application program after the manufacturing process.
Each of the plurality of configuration data, which are stored in the configuration information storage block, includes any one of internal bias information, internal logic configuration information, repair address information, and redundancy information. Repair address information may be used to point to spare memory cells to be used in place of bad memory cells. The specific number of memory cells disabled and mapped to spare memory cells due to a specific bad memory cell may be design dependent.
Initialization is performed during a power-up period in a nonvolatile memory apparatus. Part of the initialization comprises a page buffer detecting and outputting the configuration data stored in the configuration information storage block. At this time, if repair addresses are part of the configuration data, the repair addresses are stored in a repair address latch unit.
A memory device of the nonvolatile memory apparatus can be divided into a plurality of planes. Each plane includes memory blocks and the page buffer. The respective planes operate independently of one another. In general, the plurality of planes are configured in such a manner that they are sequentially activated (or selected) and operated.